55 ?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series lead-free/green sp720 general purpose esd protection - sp720 series description features ? esd interface capability for hbm standards - mil std 3015.7 ................................................. 15kv - iec 61000-4-2, direct discharge, - single input .......................................... 4kv (level 2) - two inputs in parallel ............................ 8kv (level 4) - iec 61000-4-2, air discharge ...............15kv (level 4) ? high peak current capability - iec 61000-4-5 (8/20s) ....................................... 3a - single pulse, 100s pulse width ........................ 2a - single pulse, 4s pulse width ............................ 5a ? designed to provide over-voltage protection - single-ended voltage range to ........................ +30v - differential voltage range to ............................ 15v ? fast switching ..............................................2ns risetime ? low input leakages .................................1na at 25o (typ) ? low input capacitance ....................................... 3pf (typ) ? an array of 14 scr/diode pairs ? operating temperature range ....................-40oc to 105oc applications the sp720 is an array of scr/diode bipolar structures for esd and over-voltage protection to sensitive input circuits. the sp720 has 2 protection scr/diode device structures per input. a total of 14 available inputs can be used to protect up to 14 external signal or bus lines. over-voltage protection is from the in (pins 1-7 and 9-15) to v+ or v-. the scr structures are designed for fast triggering at a threshold of one +v be diode threshold above v+ (pin 16) or a -v be diode threshold below v- (pin 8). from an in input, a clamp to v+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one v be above v+. a similar clamp to v- is activated if a negative pulse, one v be less than v-, is applied to an in input. standard esd human body model (hbm) capability is: ? microprocessor/logic input protection ? data bus protection ? analog device input protection ? voltage clamp pinout functional block diagram v+ 16 1 8 2 3 - 7 9 - 15 in in in v- rohs pb green sp720 (pdip, soic) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in in in in in in v- in v+ in in in in in in in life support note: not intended for use in life support or life saving applications the products shown herein are not designed for use in life sustaining or life saving applications unless otherwise expressly indicated. sp720 series 3pf 4kv rail clamp array
?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. 56 tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series general purpose esd protection - sp720 series absolute maximum ratings parameter rating units continuous supply voltage, (v+) - (v-) +35 v forward peak current, i in to v cc , i in to gnd (refer to figure 5) 2, 100s a electrical characteristics t a = -40 o c to 105 o c, v in = 0.5v cc , unless otherwise specifed thermal information parameter rating units thermal resistance (typical, note 1) ja o c/w pdip package 90 o c/w soic package 130 o c/w maximum storage temperature range -65 to 150 o c maximum junction temperature (plastic package) 150 o c maximum l ead temperature (soldering 20-40s) (soic lead tips only) 260 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. parameter symbol test conditions min typ max units operating voltage range, v supply = [(v+) - (v-)] v supply - 2 to 30 - v forward voltage drop: i in = 1a (peak pulse) in to v- v fwdl - 2 - v in to v+ v fwdh - 2 - v input leakage current i in -20 5 20 na quiescent supply current i quiescent - 50 200 na equivalent scr on threshold note 3 - 1. 1 - v equivalent scr on resistance v fwd /i fwd ; note 3 - 1 - input capacitance c in - 3 - pf input switching speed t on - 2 - ns note: esd ratings and capability - see figure 1, table 1 load dump and reverse battery (note 2) 1. ja is measured with the component mounted on an evaluation pc board in free air. notes: 2. in automotive and battery operated systems, the power supply lines should be externally protected for load dump and everse battery v+ and v- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the sp720 supply pins to limit reverse battery current to within the rated maximum limits. bypass capacitors of typically 0.01f or larger from the v+ and v- pins to ground are recommended. 3. refer to the figure 3 graph for defnitions of equivalent scr on threshold and scr on resistance. these characteristics are given here for thumb-rule nformation to determine peak current and dissipation under eos conditions. (application as an input clamp for over-voltage, greater than 1v be above v+ or less than -1v be below v-) figure 4. typical application of the sp720 as an input clamp for over-vol ta ge, greater than 1v be above v+ or less than -1v be bel ow v- +v cc +v cc input drivers protection circuit (1 of 14 on chip) sp720 input or signal sources in 9-15 in 1- 7 sp720 v- to +v cc linear or digital ic interf ac e v+ typical application of the sp720
57 ?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series lead-free/green sp720 general purpose esd protection - sp720 series esd capability esd capability is dependent on the application and defned test standard. the evaluation results for various test standards and methods based on figure 1 are shown in table 1. for the modifed mil-std-3015.7 condition that is defned as an in-circuit method of esd testing, the v+ and v- pins have a return path to ground and the sp720 esd capability is typically greater than 15kv from 100pf through 1.5k. by strict defnition of mil-std-3015.7 using pin-to-pin device testing, the esd voltage capability is greater than 6kv. the mil-std-3015.7 results were determined from at&t esd test lab measurements. the hbm capability to the iec 61000-4-2 standard is greater than 15kv for air discharge (level 4) and greater than 4kv for direct discharge (level 2). dual pin capability (2 adjacent pins in parallel) is well in excess of 8kv (level 4). for esd testing of the sp720 to eiaj ic121 machine model (mm) standard, the results are typically better than 1kv from 200pf with no series resistance. standard type/mode r d c d v d mil std 3015.7 modifed hbm 1.5k 100pf 15kv standard hbm 1.5k 100pf 6kv iec 61000-4-2 hbm, air discharge 330 150pf 15kv hbm, direct discharge 330 150pf 4kv hbm, direct discharge, two parallel input pins 330 150pf 8kv eiaj ic121 machine model 0k 200pf 1kv h.v. supply v d in dut c d r 1 iec 1 00 0-4-2: r 1 50 to 1 00 m r d charge switch discharge switch mil std 3015.7: r 1 1 to 10m figure 1. electr os ta tic discharge test figure 1: electrostatic discharge test table 1: esd test conditions figure 3: high current scr forward voltage drop curve figure 2: low current scr forward voltage drop curve 60 08 00 1 000 12 00 10 0 80 60 40 20 0 t a = 25c single pulse forward scr vo lta ge drop (mv) forward scr current (ma) 2.5 2 1. 5 1 0.5 0 v fwd i fwd 3 equiv . sa t. on threshold ~ 1.1v forward scr current (a) t a = 25c single pulse for wa rd scr vo lta ge drop (v) 2 1 0
?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. 58 tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series general purpose esd protection - sp720 series peak transient current capability for long duration surges the peak transient current capability rises sharply as the width of the current pulse narrows. destructive testing was done to fully evaluate the sp720s ability to withstand a wide range of transient current pulses. the circuit used to generate current pulses is shown in figure 4. the test circuit of figure 4 is shown with a positive pulse input. for a negative pulse input, the (-) current pulse input goes to an sp720 in input pin and the (+) current pulse input goes to the sp720 v- pin. the v+ to v- supply of the sp720 must be allowed to foat. (i.e., it is not tied to the ground reference of the current pulse generator.) figure 5 shows the point of overstress as defned by increased leakage in excess of the data sheet published limits. the maximum peak input current capability is dependent on the v+ to v- voltage supply level, improving as the supply voltage is reduced. values of 0, 5, 15 and 30 voltages are shown. the safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in figure 5. when adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. for comparison, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. the overstress curve is shown in figure 5 for a 15v supply condition. the dual pins are capable of 10a peak current for a 10s pulse and 4a peak current for a 1ms pulse. the complete for single pulse peak current vs. pulse width time ranging up to 1 second are shown in figure 5. + - current sense vo lt ag e probe 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 in in in in in in v- in v+ in in in in in in in + - r 1 ~ 1 0 typical sp720 v g v g adj . 10v/a typical r 1 (-) (+) c1 ~ 1 00 f c1 variable time duration current pulse genera to r figure 5. typical sp720 peak current test circuit with a variable pulse width input 0.0 01 0.01 0.1 1 peak current (a) 10 7 6 5 4 3 2 1 0 0v 5v 15v 10 0 1 000 10 9 30v 15v 8 caution: safe operating conditions limit the maximum peak current for a given pulse width to be no greater than 75% of the values shown on each curve. single pin stress curves dual pin stress curve v+ to v-supply pulse width time (ms) showing the measured point of overstress in amperes vs pulse width time in milliseconds (t a = 25 o c) figure 5: sp720 typical nonrepetitive peak current pulse capability figure 4: typical sp720 peak current test circuit with a variable pulse width input
59 ?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series lead-free/green sp720 general purpose esd protection - sp720 series ti me temperature t p t l t s(max) t s(min) 25 t p t l t s time to peak temperature preheat p rehea t ramp-up r amp-up ramp-down r amp-d o critical zone t l to t p c ritical zon e t l to t p refow condition pb C free assembly pre heat - temperature min (t s(min) ) 150c - temperature max (t s(max) ) 200c - time (min to max) (t s ) 60 C 180 secs average ramp up rate (liquidus) temp (t l ) to peak 5c/second max t s(max) to t l - ramp-up rate 5c/second max refow - temperature (t l ) (liquidus) 217c - temperature (t l ) 60 C 150 seconds peak temperature (t p ) 260 +0/-5 c time within 5c of actual peak temperature (t p ) 20 C 40 seconds ramp-down rate 5c/second max time 25c to peak temperature (t p ) 8 minutes max. do not exceed 260c soldering parameters notes: 1. controlling dimensions: inch. in case of con?ict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. symbols are de?ned in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs-3. 5. d, d1, and e1 dimensions do not include mold ?ash or protrusions. mold ?ash or protrusions shall not exceed 0. 010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0. 010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10 . corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating ba se plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) ca m bs package pdip pins 16 lead dual-in-line jedec e16.3 ms-001-bb issue d millimeters inches notes min max min max a - 5.33 - 0.210 4 a1 0.39 - 0.015 - 4 a2 2.93 4.95 0.115 0.195 - b 0.356 0.558 0.014 0.022 - b1 1. 15 1.77 0.045 0.070 8, 10 c 0.204 0.355 0.008 0.014 - d 18.66 19.68 0.735 0.775 5 d1 0.13 - 0.005 - 5 e 7.62 8.25 0.300 0.325 6 e1 6.10 7. 11 0.240 0.280 5 e 2.54 bsc 0.100 bsc - e a 7.62 bsc 0.300 bsc 6 e b - 10.92 - 0.430 7 l 2.93 3.81 0.115 0.150 4 n 16 16 9 notes: 1. controlling dimensions: inch. in case of confict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. symbols are defned in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je-dec seating plane gauge gs-3. 5. d, d1, and e1 dimensions do not include mold fash or protrusions. mold fash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and e a are measured with the leads constrained to be perpendicular to datum -c- . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). package dimensions dual-in-line plastic packages (pdip)
?2011 littelfuse, inc. specifcations are subject to change without notice. please refer to www.littelfuse.com/spa for current information. 60 tvs diode arrays (spa ? family of products) revision: june 27, 2011 sp720 lead-free/green series general purpose esd protection - sp720 series part numbering system lead plating matte tin lead material copper alloy lead coplanarity 0.004 inches (0.102mm) subsitute material silicon body material molded epoxy flammability ul94-v-0 product characteristics ordering information package dimensions small outline plastic packages (soic) notes: 1. symbols are defned in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. dimension d does not include mold fash, protrusions or gate burrs. mold fash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead fash or protrusions. interlead fash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension:millimeter. converted inch dimensions are not necessarily exact. package soic pins 16 jedec m16.15 (jedec ms-012-ac issue c) millimeters inches notes min max min max a 1.35 1.75 0.0532 0.0688 - a1 0.10 0.25 0.0040 0.0098 - b 0.33 0.51 0.013 0.020 9 c 0.19 0.25 0.0075 0.0098 - d 9.80 10.00 0.3859 0.3937 3 e 3.80 4.00 0.1497 0.1574 4 e 1.27 bsc 0.050 bsc - h 5.80 6.20 0.2284 0.2440 - h 0.25 0.50 0.0099 0.0196 5 l 0.40 1.27 0.016 0.050 6 n 16 16 7 0o 8o 0o 8o - notes: 1. symbols are de?ned in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. dimension ?d? does not include mold ?ash, protrusions or gate burrs. mold ?ash, protrusion and gate bur rs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead ?ash or protrusions. interlead ?ash and protrusions shall not exceed 0.25mm (0. 010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.0 14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10 . controlling dimension:millimeter. converted inch dimensions are not necessarily exact. index area e d n 12 3 -b- 0.25(0.0 10 )c am bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.0 10 )b m m part number temp. range (oc) package environmental informaton marking min. order SP720APP -40 to 105 16 ld pdip lead-free 720app 1500 sp720abg -40 to 105 16 ld soic green 720abg 1920 sp720abtg -40 to 105 16 ld soic tape and reel green 720abg 2500 sp 720 ab tg series package p=lead free g = green tg= tape and reel / green ab = 16 ld soic ap = 16 ld pdip silicon protection array (spa tm ) family of tvs diode arrays see ordering information section for specific options available
|
